n-Dimensional Processor Arrays with Optical dBuses

  • Authors:
  • Guoping Liu;Kyungsook Y. Lee;Harry F. Jordan

  • Affiliations:
  • J. D. Edwards World Source Company, One Technology Way, Denver, CO 80237;Department of Mathematics and Computer Science, University of Denver, Denver, CO 80208-0189;Optoelectronics Computing Systems Center, University of Colorado at Boulder, Boulder, CO 80309-0425

  • Venue:
  • The Journal of Supercomputing
  • Year:
  • 2000

Quantified Score

Hi-index 0.00

Visualization

Abstract

dBus-array(k, n) is an n-dimensional processor array of k^n nodes connected via k^n−1 dBuses. A dBus is a unidirectional bus which receives signals from a set of k nodes (input set), and transmits signals to a different set of k nodes (output set). Two optical implementations of the dBus-array(k, n) are discussed. One implementation uses the wavelength division multiplexing as in the wavelength division multiple access channel hypercube WMCH [7]. WMCH(k, n) and dBus-array(k, n) have the same diameter and about the same average internode distance, while the dBus-array requires only one tunable transmitter/receiver per node, compared to n tunable transmitters/receivers per node for the WMCH. The other implementation uses one fixed-wavelength transmitter/receiver per node and the dilated slipped banyan switching network (DSB) [17] to combine time division and wavelength division multiplexing.