A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

  • Authors:

  • Jiyang Kang;Jongbok Lee;Wonyong Sung

  • Affiliations:

  • School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea;Department of Information and Communications Engineering, Hansung University, 389, Samsun-Dong 2-Ga, Sungbuk-Gu, Seoul 136-792, Republic of Korea;School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2001

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Abstract

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such as many general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, a QCELP vocoder, and an MPEG video decoder. The effects of CPU clock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.