Scanline surfacing: building separating surfaces from planar contours

  • Authors:
  • David Weinstein

  • Affiliations:
  • Scientific Computing and Imaging Institute, School of Computing, University of Utah

  • Venue:
  • Proceedings of the conference on Visualization '00
  • Year:
  • 2000

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Abstract

This paper presents several low-latency mixed-timing FIFO designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The design are then adapted to work between systems with very long interconnection delays, by migrating a singel-clock solution by carloni et al. (for “latency-insensitive” protocols) to mixed-timing domains. THe new designs can be made arbitrarily robust with regard to metastability and interface operating speeds. Initials simulationsfor both latency and throughput are promising.