A multi-level strategy for software power estimation

Authors:
C. Brandolese;W. Fornaciari;L. Pomante;F. Salice;D. Sciuto
Affiliations:
Politecnico di Milano, P.zza L. da Vinci, 32 - 20133 Milano, Italy;Politecnico di Milano, P.zza L. da Vinci, 32 - 20133 Milano, Italy;Politecnico di Milano, P.zza L. da Vinci, 32 - 20133 Milano, Italy;Politecnico di Milano, P.zza L. da Vinci, 32 - 20133 Milano, Italy;Politecnico di Milano, P.zza L. da Vinci, 32 - 20133 Milano, Italy
Venue:
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Year:
2000

Citing 2
Cited 3

Power analysis of embedded software: a first step towards software power minimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
High-level power modeling, estimation, and optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Source-level execution time estimation of C programs

Proceedings of the ninth international symposium on Hardware/software codesign
An analytical model for predicting the remaining battery capacity of lithium-ion batteries

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated, retargetable back-annotation for host compiled performance and power modeling

Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper a comprehensive methodology for software power estimation is presented. The methodology is supported by rigorous mathematical models of power consumption at three different levels of abstraction. The methodology has been validated in a complete framework developed within the TOSCA co-design environment.