A low power direct digital frequency synthesizer with 60 dBc spectral purity

Authors:
J. M.P. Langlois;D. Al-Khalili
Affiliations:
Royal Military College of Canada, Kingston, Ontario, Canada;Royal Military College of Canada, Kingston, Ontario, Canada
Venue:
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Year:
2002

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Abstract

We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 &mgr;m CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ROM or multipliers are used, but an external DAC is required if an analog output is desired. Power consumption is 10 mW for a 100 MHz clock, which is significantly less than figures reported previously. System complexity is greatly reduced by using an efficient linear interpolation scheme to approximate a sinusoid function. This has resulted in silicon area utilization of 0.011 mm2. The design would be suitable as an IP core in a low power digital RF transceiver ASIC.