Virtual simulation of distributed IP-based designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Robust FPGA intellectual property protection through multiple small watermarks
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Using general-purpose programming languages for FPGA design
Proceedings of the 37th Annual Design Automation Conference
A Web-CAD methodology for IP-core analysis and simulation
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Principles of VERILOG PLI
A CAD Suite for High-Performance FPGA Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain FPGA circuits directly within a web browser. Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of application-specific circuits. Applets can be customized to provide varying levels of IP visibility and functionality as needed by both customer and vendor.