Power conscious fixed priority scheduling for hard real-time systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Heterogeneous modeling and simulation of embedded systems in El Greco
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dynamic voltage scaling and power management for portable systems
Proceedings of the 38th annual Design Automation Conference
Energy efficient fixed-priority scheduling for real-time systems on variable voltage processors
Proceedings of the 38th annual Design Automation Conference
Dynamic voltage scheduling technique for low-power multimedia applications using buffers
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
IEEE Design & Test
Specification and design of reactive systems
Specification and design of reactive systems
Power optimization of variable-voltage core-based systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pareto-optimization-based run-time task scheduling for embedded systems
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Computers
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
System-scenario-based design of dynamic embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 50th Annual Design Automation Conference
Microprocessors & Microsystems
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This paper presents a method of intra-task dynamic voltage scaling (DVS) for SoC design with hierarchical FSM and synchronous dataflow model (in short, HFSM-SDF model). To have an optimal intra-task DVS, exact execution paths need to be determined in compile time or runtime. In general programs, since determining exact execution paths in compile time or runtime is not possible, existing methods assume worst/average-case execution paths and take static voltage scaling approaches. In our work, we exploit a property of HFSM-SDF model to calculate exact execution paths in runtime. With the information of exact execution paths, our DVS method can calculate exact remaining workload. The exact workload enables to calculate optimal voltage level which gives optimal energy consumption while satisfying the given timing constraint. Experiments show the effectiveness of the presented method in low-power design of an MPEG4 decoder system.