Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Sizing synchronization queues: a case study in higher level synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Concepts and Notations for Concurrent Programming
ACM Computing Surveys (CSUR)
Guarded commands, nondeterminacy and formal derivation of programs
Communications of the ACM
Design of a separable transition-diagram compiler
Communications of the ACM
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
IEEE Design & Test
System synthesis via hardware-software co-design
System synthesis via hardware-software co-design
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Synthesis of systems containing application-specific as well as re-programmable components, such as off-the-shelf microprocessors, provides a promising approach to realization of complex systems using a minimal amount of application-specific hardware while still meeting the required performance constraints. We describe an approach to synthesis of such hardware-software systems starting from behavioral description as input. The input system model is partitioned into hardware and software components based on imposed performance constraints. Synchronization between various elements of a mixed system design is one of the key issues that any synthesis system must address. In this paper, we consider software and interface synchronization schemes that facilitate communication between system components. We present tools to perform synthesis and simulation of a system description into hardware and software components. In particular, we describe a program, Poseidon, that performs concurrent event-driven simulation of multiple functional modules implemented either as a program or as behavioral or structural hardware models. Input to Poseidon consists of description of interacting functional models with their respective clock cycle times and the interface synchronization scheme chosen by the partitioner. The resulting software component is assumed to be implemented for the DLX machine, a load/store microprocessor. We present simulation examples and design of a graphics controller demonstrate the feasibility of mixed system synthesis.