A ray-slice-sweep volume rendering engine
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
GI-cube: an architecture for volumetric global illumination and rendering
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
3d Computer Graphics
Handbook of Computer Vision and Applications with Cdrom
Handbook of Computer Vision and Applications with Cdrom
Ray Casting Architectures for Volume Visualization
IEEE Transactions on Visualization and Computer Graphics
Memory and Processing Architecture for 3D Voxel-Based Imagery
IEEE Computer Graphics and Applications
SCCG '03 Proceedings of the 19th spring conference on Computer graphics
GW4: an FPGA-driven image segmentation algorithm
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
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Computer graphics algorithms and algorithms used in image processing are generally computationally expensive. This fact is the reason why people struggle to accelerate such algorithms using any reasonable means. The traditional sources of speedup are faster processors, parallelism, or dedicated hardware. Development in digital circuit technology, especially rapid development of Field Programmable Gate Arrays (FPGA), offers alternative way to acceleration. Current FPGA chips are capable of running graphics algorithms at the speed comparable to dedicated graphics chips. At the same time they are configurable not only using schematics diagram but also through high-level programming languages, e.g. VHDL. The contribution addresses these issues, general development in the area, and shows examples of hardware platforms and algorithms that can be implemented on such platforms.