Low Power Digital CMOS Design
Design and analysis of a second order phase locked loops (PLLs)
TELE-INFO'06 Proceedings of the 5th WSEAS international conference on Telecommunications and informatics
| Hi-index | 0.00 |
Phase Frequency Detectors (PFDs) for use in clock distribution PLLs and Phase Detectors (PDs) for clock recovery PLLs that we have proposed recently to achieve high performance are reviewed and discussed. For the PFD, operating speed limitation and phase detecting characteristics are improved with two kinds of approaches, i.e., gate/logic design and configuration design. For the PD, a simple compensation technique to prevent the deterioration of the phase detecting characteristics by D-F/F and a new PD with delay cell of VCO replica are proposed to reduce the jitter caused by PD. By SPICE simulations and experiments, it is confirmed that the maximum operating speed of PFD is improved to more than twice of conventional one and the jitter caused by PD is reduced to a minimum level.