A Symbolic Pole/Zero Extraction Methodology Based on Analysis of Circuit Time-Constants

Authors:
O. Guerra;J. D. Rodríguez-García;F. V. Fernández;A. Rodríguez-Vázquez
Affiliations:
Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edificio CNM, Avda. Reina Mercedes s/n., E-41012-Sevilla, Spain Tel.: 34 955056666, Fax: 34 955056686;Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edificio CNM, Avda. Reina Mercedes s/n., E-41012-Sevilla, Spain Tel.: 34 955056666, Fax: 34 955056686;Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edificio CNM, Avda. Reina Mercedes s/n., E-41012-Sevilla, Spain Tel.: 34 955056666, Fax: 34 955056686 and & ...;Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edificio CNM, Avda. Reina Mercedes s/n., E-41012-Sevilla, Spain Tel.: 34 955056666, Fax: 34 955056686 and & ...
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2002

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Abstract

This paper introduces a methodology for symbolic pole/zero extraction based on the formulation of the time-constant matrix of the circuits. This methodology incorporates approximation techniques specifically devoted to achieve an optimum trade-off between accuracy and complexity of the symbolic root expressions. The capability to efficiently handle even large circuits will be demonstrated through several practical circuits.