Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
The algorithmic beauty of plants
The algorithmic beauty of plants
PROOF: an architecture for rendering in object space
Advances in computer graphics hardware III
PixelFlow: high-speed rendering using image composition
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
Image-composition architectures for real-time image generation
Image-composition architectures for real-time image generation
Parallel processing image synthesis and anti-aliasing
SIGGRAPH '81 Proceedings of the 8th annual conference on Computer graphics and interactive techniques
Image composition methods for sort-last polygon rendering on 2-D mesh architectures
PRS '95 Proceedings of the IEEE symposium on Parallel rendering
Image Composition Schemes for Sort-Last Polygon Rendering on 2D Mesh Multicomputers
IEEE Transactions on Visualization and Computer Graphics
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Previous pixel-merging algorithms have required special-purpose networks, and use more network bandwidth than is necessary. We developed an algorithm that merges pixels on shared-memory bus multiprocessors, using an existing bus. Analysis and simulations suggest that it uses less bus bandwidth than other algorithms. We based our algorithm on the snooping cache-coherency protocols on which a number of shared-memory multiprocessors have been based. In these architectures, each processor keeps its cache consistent with other processors' memories by listening (snooping) on a shared bus over which memory updates are written. Snooping maintains consistent globally shared memory. This algorithm assists graphics rendering by letting processors compare pixel values and delete those pixels that do not contribute to the final image. This reduces network bandwidth requirements and eliminates the need for a special-purpose network.