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This paper reports some of the interesting properties and relationships of a nongroup Cellular Automata (CA) and its dual. A special class of nongroup Cellular Automata denoted as D1*CA is analytically investigated. Based on such analysis, D1*CA has been proposed as an ideal test machine which can be efficiently embedded in a finite state machine to enhance the testability of the synthesized design. A state encoding algorithm has been formulated to embed the D1*CA based test machine in the synthesized FSM while minimizing the hardware overhead. The unique state transition properties of D1*CA are then used in designing an easy testing scheme for the FSM. Experiments on FSM benchmarks have shown that the scheme achieves 100% coverage of all single stuck-at faults at the cost of hardware overhead and circuit delay that are comparable, if not better, to that incurred for scan path based designs. However, the major advantage of the scheme is the significant reduction of test time overhead due to integration of an embedded test machine in the design at the synthesis phase.