Memory Bandwidth Analysis of Hierarchical Multiprocessors using Model Decomposition and Steady-State Flow Analysis

Authors:
S. M. Mahmud;L. T. Samaratunga
Affiliations:
-;-
Venue:
IEEE Transactions on Parallel and Distributed Systems
Year:
1994

Citing 4
Cited 1

Bandwidth availability of multiple-bus multiprocessors

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Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model

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Performance Analysis of a Generalized Class of M-Level Hierarchical Multiprocessor Systems

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CPMBK: An improved cluster-based interconnection network

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Abstract

For memory bandwidth analysis, researchers generally discard requests that are notaccepted during a memory cycle. This assumption simplifies the analysis and producesnegligible discrepancies with actual results for a system with a non-hierarchicalinterconnection network. However, the assumption, "the requests that are not occupiedduring a memory cycle are discarded," cannot be used for a multiprocessor system with ahierarchical interconnection network (HIN), because the error introduced assumption canbe several orders of magnitude higher than the actual bandwidth. An improved analyticalmodel to determine the bandwidth of a HIN-based system is presented.