A finite state machine based format model of software pipelined loops with conditions

Authors:
Dragan Milicev;Zoran Jovanovic
Affiliations:
Department of Computer Science, Faculty of Electrical Engineering, University of Belgrade ,POB 35-54, 11120 Belgrade, YUGOSLAVIA;Department of Computer Science, Faculty of Electrical Engineering, University of Belgrade ,POB 35-54, 11120 Belgrade, YUGOSLAVIA
Venue:
Progress in computer research
Year:
2001

Citing 29
Cited 0

Compilers: principles, techniques, and tools

Compilers: principles, techniques, and tools
The program dependence graph and its use in optimization

ACM Transactions on Programming Languages and Systems (TOPLAS)
Optimal loop parallelization

PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Software pipelining: an effective scheduling technique for VLIW machines

PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-Offs

Computer
A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture

Selected papers of the second workshop on Languages and compilers for parallel computing
On optimal parallelization of arbitrary loops

Journal of Parallel and Distributed Computing
GURPR*: a new global software pipelining algorithm

MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Limits of control flow on parallelism

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Code generation schema for modulo scheduled loops

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Enhanced modulo scheduling for loops with conditional branches

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Reverse If-Conversion

PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Instruction-level parallel processing: history, overview, and perspective

The Journal of Supercomputing - Special issue on instruction-level parallelism
Iterative modulo scheduling: an algorithm for software pipelining loops

MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Compiler transformations for high-performance computing

ACM Computing Surveys (CSUR)
Parallelizing Iterative Loops with Conditional Branching

IEEE Transactions on Parallel and Distributed Systems
Modulo scheduling with multiple initiation intervals

Proceedings of the 28th annual international symposium on Microarchitecture
Software pipelining loops with conditional branches

Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
GPMB—software pipelining branch-intensive loops

MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
A compilation technique for software pipelining of loops with conditional jumps

MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Split-path enhanced pipeline scheduling for loops with control flows

MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Conversion of control dependence to data dependence

POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Requirements for Optimal Execution of Loops with Tests

IEEE Transactions on Parallel and Distributed Systems
Perfect Pipelining: A New Loop Parallelization Technique

ESOP '88 Proceedings of the 2nd European Symposium on Programming
A Formal Model of Software Pipelining Loops with Conditions

IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Percolation Scheduling: A Parallel Compilation Technique

Percolation Scheduling: A Parallel Compilation Technique
Predicated Software Pipelining Technique for Loops with Conditions

IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Formal languages and their relation to automata

Formal languages and their relation to automata

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper addresses the problem of parallelizing loops with conditional branches, in the context of software pipelining. A new formal approach to this problem is proposed, called the predicated Software Pipelining (PSP) model. The PSP model represents execution of a loop with conditional branches as trasitions of a finite state machine Each node of the state machine is composed of operations of one parallelized loop iteration. The rules of operation movements between nodes in the PSP model and discribed. The model represents a new theoritical framework for further investigation of inherent properties of these loops, as well as a basis for novel scheduling techniques.