Advanced compiler optimizations for supercomputers
Communications of the ACM - Special issue on parallelism
Requirements for optimal execution of oops with tests
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Incremental performance contributions of hardware concurrency extraction techniques
Proceedings of the 1st International Conference on Supercomputing
On optimal parallelization of arbitrary loops
Journal of Parallel and Distributed Computing
A Theory of Reduced and Minimal Procedural Dependencies
IEEE Transactions on Computers
Enhancing concurrent program execution with eager evaluation
Enhancing concurrent program execution with eager evaluation
Concurrency Extraction Via Hardware Methods Executing the Static Instruction Stream
IEEE Transactions on Computers
A compilation technique for software pipelining of loops with conditional jumps
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
GURPR—a method for global software pipelining
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
On the combination of hardware and software concurrency extraction methods
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Perfect Pipelining: A New Loop Parallelization Technique
ESOP '88 Proceedings of the 2nd European Symposium on Programming
Hardware extraction of low-level concurrency from sequential instruction streams (parallelism, implementation, architecture, dependencies, semantics)
On program restructuring, scheduling, and communication for parallel processor systems
On program restructuring, scheduling, and communication for parallel processor systems
Extraction of massive instruction level parallelism
ACM SIGARCH Computer Architecture News
A macrotask-level unlimited speculative execution on multiprocessors
ICS '95 Proceedings of the 9th international conference on Supercomputing
GPMB—software pipelining branch-intensive loops
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Optimal software pipelining of loops with control flows
ICS '02 Proceedings of the 16th international conference on Supercomputing
A finite state machine based format model of software pipelined loops with conditions
Progress in computer research
A First Step Towards Time Optimal Software Pipelining of Loops with Control Flows
CC '01 Proceedings of the 10th International Conference on Compiler Construction
Time optimal software pipelining of loops with control flows
International Journal of Parallel Programming
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Both the efficient execution of branch intensive code and knowing the bounds on the same are important issues in computing in general and supercomputing in particular. In prior work, it has been suggested that the hardware needed to execute code with branches optimally is exponentially dependent on the total number of dynamic branches executed, this number of branches being proportional at least to the number of iterations of the loop. For classes of code taking at least one cycle per iteration to execute, this is not the case. For loops containing one test (normally in the form of a Boolean recurrence of order one), it is shown that the hardware necessary varies from exponential to polynomial in the length of the dependence cycle L, while execution time varies from one time cycle per iteration to less than L time cycles per iteration; the variation depends on specific code dependences. These results bring the eager evaluation of imperative code closer to fruition.