An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers
HPSm, a high performance restricted data flow architecture having minimal functionality
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
HPS, a new microarchitecture: rationale and introduction
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
The program dependence graph and its use in optimization
ACM Transactions on Programming Languages and Systems (TOPLAS)
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Modeling the effects of instruction queue loading on a static instruction stream micro-architecture
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Desirable code transformations for a concurrent machine
Selected papers of the second workshop on Languages and compilers for parallel computing
Concurrency Extraction Via Hardware Methods Executing the Static Instruction Stream
IEEE Transactions on Computers
On the combination of hardware and software concurrency extraction methods
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Fundamental Structures of Computer Science
Fundamental Structures of Computer Science
Incremental Performance Contributions of Hardware Concurrency Extraction Techniques
Proceedings of the 1st International Conference on Supercomputing
Representation and detection of concurrency using ordering-matrices.
Representation and detection of concurrency using ordering-matrices.
Hardware extraction of low-level concurrency from sequential instruction streams (parallelism, implementation, architecture, dependencies, semantics)
Concurrency Extraction Via Hardware Methods Executing the Static Instruction Stream
IEEE Transactions on Computers
Data path issues in a highly concurrent machine
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Extraction of massive instruction level parallelism
ACM SIGARCH Computer Architecture News
Disjoint eager execution: an optimal form of speculative execution
Proceedings of the 28th annual international symposium on Microarchitecture
Branch Effect Reduction Techniques
Computer
Requirements for Optimal Execution of Loops with Tests
IEEE Transactions on Parallel and Distributed Systems
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A reduced set of procedural dependencies is presented which is necessary and sufficient to describe all procedural dependencies in standard imperative codes. Hence, the set is minimal. In conjunction with reduced data dependencies, this set forms a set of minimal semantic dependencies for all traditional code. It is also shown that all forward branches in structured code are procedurally independent. The effects of limited hardware are also addressed. A possible implementation of a machine enforcing just the minimal procedural dependencies is described.