Modeling the effects of instruction queue loading on a static instruction stream micro-architecture

Authors:
J. H. Jacobs;A. K. Uht;R. C. Ord
Affiliations:
Orincon Corporation of San Diego, Calif.;University of California, San Diego, Dept. of Computer Science and Engineering, C-014, La Jolla, California;University of California, San Diego, Dept. of Computer Science and Engineering, C-014, La Jolla, California
Venue:
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Year:
1988

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Abstract

Increased processor performance requires the exploitation of the parallelism that exists within the instruction stream and within the processor itself: A static instruction stream micro-architecture, CONDEL, extracts and uses the machine instruction level concurrency implicit in the instruction stream. A major source of intraprocessor parallelism is the overlap of instruction execution with instruction loading. The effect of several methods of utilizing the execution/loading parallelism within the static instruction stream machine are studied: pipelining, buffered pipelining, branch buffering and instruction load limiting. The results of incorporating the different methods into the micro-architecture are shown. In addition, the results provide a more realistic performance comparison with conventional machine designs than the upper limits presented in previous work.