Processor Allocation for Horizontal and Vertical Parallelism and Related Speedup Bounds
IEEE Transactions on Computers
Compiler Optimizations for Enhancing Parallelism and Their Impact on Architecture Design
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Requirements for optimal execution of oops with tests
ICS '88 Proceedings of the 2nd international conference on Supercomputing
On the combination of hardware and software concurrency extraction methods
ACM SIGMICRO Newsletter
Modeling the effects of instruction queue loading on a static instruction stream micro-architecture
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
A Theory of Reduced and Minimal Procedural Dependencies
IEEE Transactions on Computers
Effects of building blocks on the performance of super-scalar architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Concurrency Extraction Via Hardware Methods Executing the Static Instruction Stream
IEEE Transactions on Computers
Data path issues in a highly concurrent machine
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Ideograph/Ideogram: framework/hardware for eager evaluation
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
On the combination of hardware and software concurrency extraction methods
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Disjoint Eager Execution: what it is / what it is not
ACM SIGARCH Computer Architecture News
Requirements for Optimal Execution of Loops with Tests
IEEE Transactions on Parallel and Distributed Systems
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