An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers
On the combination of hardware and software concurrency extraction methods
ACM SIGMICRO Newsletter
Modeling the effects of instruction queue loading on a static instruction stream micro-architecture
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
A Theory of Reduced and Minimal Procedural Dependencies
IEEE Transactions on Computers
Concurrency Extraction Via Hardware Methods Executing the Static Instruction Stream
IEEE Transactions on Computers
On the combination of hardware and software concurrency extraction methods
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Disjoint Eager Execution: what it is / what it is not
ACM SIGARCH Computer Architecture News
Representation of Concurrency with Ordering Matrices
IEEE Transactions on Computers
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