Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Computer
A layered emulator for design evaluation of MIMD multiprocessors with shared memory
Volume I: Parallel architectures on PARLE: Parallel Architectures and Languages Europe
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Interconnection Networks for Parallel and Distributed Processing
Interconnection Networks for Parallel and Distributed Processing
A cache consistency protocol for multiprocessors with multistage networks
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Teaching a course in parallel processing with limited resources
SIGCSE '91 Proceedings of the twenty-second SIGCSE technical symposium on Computer science education
LAPACK: a portable linear algebra library for high-performance computers
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Synchronization and cache coherence in computer design
Journal of Computing Sciences in Colleges
Circulating shared-registers for multiprocessor systems
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 4.10 |
The techniques that can be used to design a memory system that reduces the impact of contention are examined. To exemplify the techniques, the implementations and the design decisions taken in each are reviewed. The discussion covers memory organization, interconnection networks, memory allocation, cache memory, and synchronization and contention. The multiprocessor implementations considered are C.mmp, CM*, RP3, Alliant FX, Cedar, Butterfly, SPUR, Dragon, Multimax, and Balance.