Genetic programming: on the programming of computers by means of natural selection
Genetic programming: on the programming of computers by means of natural selection
Parallel genetic programming: a scalable implementation using the transputer network architecture
Advances in genetic programming
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Studying the Influence of Communication Topology and Migration on Distributed Genetic Programming
EuroGP '01 Proceedings of the 4th European Conference on Genetic Programming
A Distributed Computing Environment for Genetic Programming Using MPI
Proceedings of the 7th European PVM/MPI Users' Group Meeting on Recent Advances in Parallel Virtual Machine and Message Passing Interface
Automated synthesis of analog electrical circuits by means ofgenetic programming
IEEE Transactions on Evolutionary Computation
Explorations in design space: unconventional electronics designthrough artificial evolution
IEEE Transactions on Evolutionary Computation
A circuit representation technique for automated circuit design
IEEE Transactions on Evolutionary Computation
An Empirical Study of Multipopulation Genetic Programming
Genetic Programming and Evolvable Machines
Multi-FPGA systems synthesis by means of evolutionary computation
GECCO'03 Proceedings of the 2003 international conference on Genetic and evolutionary computation: PartII
| Hi-index | 0.00 |
We present results on the application of a new methodology based on Parallel and Distributed Genetic Programming (PADGP). The aim for the methodology we present is to automatically perform the placement and routing of circuits on reconfigurable hardware. The system has been successfully applied to some benchmark problems. For each of the problems we have dealt with, the methodology is capable of finding several solutions. The results show the methodology's feasibility for addressing the problem of placement and routing on FPGAs.