Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
The priority-based coloring approach to register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
The DARPA image understanding benchmark for parallel computers
Journal of Parallel and Distributed Computing
Enhanced modulo scheduling for loops with conditional branches
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
ACM Computing Surveys (CSUR)
Resource-Constrained Software Pipelining
IEEE Transactions on Parallel and Distributed Systems
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
HPCN Europe '97 Proceedings of the International Conference and Exhibition on High-Performance Computing and Networking
Aggressive Loop Unrolling in a Retargetable Optimizing Compiler
CC '96 Proceedings of the 6th International Conference on Compiler Construction
A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops
CC '98 Proceedings of the 7th International Conference on Compiler Construction
Register File Design Considerations in Dynamically Scheduled Processors
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
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When Image Processing Programs (IPP) are targeted to Instruction Level Parallel architectures that perform dynamic instruction scheduling, register allocation is the key action to expose the high parallelism degree typically present in the loops of such programs. This paper presents two main contributions to the register allocation for IPP loop parallelization: i) a framework to identify the inefficiencies of the two basic approaches to register allocation - the first based on compiling techniques and the second based on hardware mechanisms for register renaming; ii) a novel technique that eliminates the inefficiencies of both approaches. Some experimental results show the effectiveness of this technique.