Implementation of Givens QR-Decomposition in FPGA

Authors:
Anatoli Sergyienko;Oleg Maslennikov
Affiliations:
-;-
Venue:
PPAM '01 Proceedings of the th International Conference on Parallel Processing and Applied Mathematics-Revised Papers
Year:
2001

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Abstract

A new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derivedusing methodof mapping regular algorithms using affine transformations of the algorithm graph. The methodsupp orts pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of this structure in the Xilinx Virtex FPGA devices is presented.