Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Modalities for model checking: branching time logic strikes back
Science of Computer Programming
On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Handbook of theoretical computer science (vol. B)
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Synthesis of concurrent systems for an atomic read/atomic write model of computation
PODC '96 Proceedings of the fifteenth annual ACM symposium on Principles of distributed computing
Synthesis of concurrent systems with many similar processes
ACM Transactions on Programming Languages and Systems (TOPLAS)
Synthesis of fault-tolerant concurrent programs
PODC '98 Proceedings of the seventeenth annual ACM symposium on Principles of distributed computing
Synthesis of Communicating Processes from Temporal Logic Specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Concurrent control with “readers” and “writers”
Communications of the ACM
Selected writings on computing: a personal perspective
Selected writings on computing: a personal perspective
A Discipline of Programming
On the Synthesis of an Asynchronous Reactive Module
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
Synthesizing Processes and Schedulers from Temporal Specifications
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Realizability and Synthesis of Reactive Modules
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
An algorithmic framework for synthesis of concurrent programs
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
Efficiently verifiable conditions for deadlock-freedom of large concurrent programs
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Revising UNITY programs: possibilities and limitations
OPODIS'05 Proceedings of the 9th international conference on Principles of Distributed Systems
CBSE'06 Proceedings of the 9th international conference on Component-Based Software Engineering
| Hi-index | 0.00 |
We present a tractable method for synthesizing arbitrarily large concurrent programs from specifications expressed in temporal logic. Our method does not explicitly construct the global state transition diagram of the program to be synthesized, and thereby avoids state explosion. Instead, it constructs a state transition diagram for each pair of component processes (of the program) that interact. This "pair-program" embodies all possible interactions of the two processes. Our method proceeds in two steps. First, we construct a pair-program for every pair of "connected" processes, and analyze these pair-programs for desired correctness properties. We then take the "pair processes" of the pair-programs, and "compose" them in a certain way to synthesize the large concurrent program. We establish a "large model" theorem which shows that the synthesized large program inherits correctness properties from the pair-programs.