Structured Formal Verification of a Fragment of the IBM S/390 Clock Chip

Authors:
Alfons Geser;Wolfgang Küchlin
Affiliations:
-;-
Venue:
FM-Trends 98 Proceedings of the International Workshop on Current Trends in Applied Formal Method: Applied Formal Methods
Year:
1998

Citing 18
Cited 0

Refutational theorem proving using term-rewriting systems

Artificial Intelligence
Automatic Verification of Sequential Circuits Using Temporal Logic

IEEE Transactions on Computers
Application of term rewriting techniques to hardware design verification

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Termination of rewriting

Journal of Symbolic Computation
The design of a microprocessor

The design of a microprocessor
A specification of the Intel 8085 microprocessor: a case study

Algebraic methods: theory, tools and applications
Formal verification of the Sobel image processing chip

Current trends in hardware verification and automated theorem proving
Graph rewriting: an algebraic and logic approach

Handbook of theoretical computer science (vol. B)
Rewrite systems

Handbook of theoretical computer science (vol. B)
Algebraic specification

Handbook of theoretical computer science (vol. B)
Symbolic Boolean manipulation with ordered binary-decision diagrams

ACM Computing Surveys (CSUR)
The term rewriting approach to automated theorem proving

Journal of Logic Programming
Term graph rewriting: theory and practice

Term graph rewriting: theory and practice
PSATO: a distributed propositional prover and its application to quasigroup problems

Journal of Symbolic Computation - Special issue on parallel symbolic computation
Modular Verification of SRT Division

CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
PVS: Combining Specification, Proof Checking, and Model Checking

CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Verification of the Sparrow Processor

ECBS '96 Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems
Symbolic Model Checking for Sequential Circuit Verification

Symbolic Model Checking for Sequential Circuit Verification

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a simple and powerful method for formal verification of hardware that exploits hardwcire symmetries. We illustrate the method at an industrial example: a fragment of the IBM S/390 Clock Chip.