Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
URPR—An extension of URCR for software pipelining
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
Towards a microprogramming language schema
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
An improvement of trace scheduling for global microcode compaction
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
A retargetable compiler for a high-level microprogramming language
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
A model of clocked micro-architectures for firmware engineering and design automation applications
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
An axiomatization of low-level parallelism in microarchitectures
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Retargetable code generation and optimization using attribute grammars
Retargetable code generation and optimization using attribute grammars
Design and construction of a virtual machine resource binding language
Design and construction of a virtual machine resource binding language
Local code generation and compaction in optimizing microcode compilers
Local code generation and compaction in optimizing microcode compilers
Bulldog: a compiler for vliw architectures (parallel computing, reduced-instruction-set, trace scheduling, scientific)
A critical analysis of the global optimization problem for horizontal microcode (phase-coupled, compaction, code motion, compilation)
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We discuss the integration of a trace scheduling optimizer into a retargetable optimizing microcode compiler that handles complex timing relations. The trace scheduler requires no special treatment when retargeting the compiler, being constructed from machine independent algorithms that extract target micro-architecture details from a machine description used by the other compiler processes. We focus on the machine independent basis of the trace scheduler and demonstrate it on a hypothetical micro-architecture.