Design and Implementation of FPGA Circuits for High Speed Network Monitors

Authors:
Masayuki Kirimura;Yoshifumi Takamoto;Takanori Mori;Keiichi Yasumoto;Akio Nakata;Teruo Higashino
Affiliations:
-;-;-;-;-;-
Venue:
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Year:
2002

Citing 10
Cited 0

Computer networks (3rd ed.)

Computer networks (3rd ed.)
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization

Proceedings of the 37th Annual Design Automation Conference
Bro: a system for detecting network intruders in real-time

Computer Networks: The International Journal of Computer and Telecommunications Networking
Towards trapping wily intruders in the large

Computer Networks: The International Journal of Computer and Telecommunications Networking - Special issue on recent advances in intrusion detection systems
On the effectiveness of route-based packet filtering for distributed DoS attack prevention in power-law internets

Proceedings of the 2001 conference on Applications, technologies, architectures, and protocols for computer communications
Denial-of-Service Attacks Rip the Internet

Computer
Hardware synthesis from protocol specifications in LOTOS

FORTE XI / PSTV XVIII '98 Proceedings of the FIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XI) and Protocol Specification, Testing and Verification (PSTV XVIII)
Design of the APIC: A high performance ATM host-network interface chip

INFOCOM '95 Proceedings of the Fourteenth Annual Joint Conference of the IEEE Computer and Communication Societies (Vol. 1)-Volume - Volume 1
OC3MON: Flexible, Affordable, High Performance Staistics Collection

LISA '96 Proceedings of the 10th USENIX conference on System administration
Inferring internet denial-of-service activity

SSYM'01 Proceedings of the 10th conference on USENIX Security Symposium - Volume 10

Quantified Score

Hi-index	0.00

Visualization

Abstract

Due to the recent progress of the Internet, we need high-speed network monitors which can observe millions of packets per second. Since several types of network attacks occur, we need to modify monitoring facilities and their capacities depending on monitoring items and network speed. In this paper, we propose (1) a methodology for designing and implementing such network monitors flexibly and (2) a high-level synthesis technique which automatically synthesizes FPGA circuits from specifications of network monitors in a model called concurrent synchronous EFSMs. The proposed technique makes it possible to synthesize an FPGA circuit suitable for given monitoring items and parameters where the designer need not consider about how pipe-line processing and parallel processing should be adopted. We have developed a tool to automatically derive FPGA circuits and evaluated the speed and size of derived circuits.