aItPm: a strategy for integrating IP with ATM
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Efficient data layout, scheduling and playout control in MARS
Multimedia Systems - Special issue on the fifth workshop on network and operating system support for digital audio and video 1995 (NOSSDAV)
A parallel embedded-processor architecture for ATM reassembly
IEEE/ACM Transactions on Networking (TON)
Supporting high-performance I/O in QoS-enabled ORB middleware
Cluster Computing
Improving End System Performance for Multimedia Applicationsover High Bandwidth Networks
Multimedia Tools and Applications
Design and Implementation of FPGA Circuits for High Speed Network Monitors
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
The APIC Approach to High Performance Network Interface Design: Protected DMA and Other Techniques
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Operating system support for high-performance, real-time CORBA
IWOOOS '96 Proceedings of the 5th International Workshop on Object Orientation in Operating Systems (IWOOOS '96)
Applying optimization principle patterns to design real-time ORBs
COOTS'99 Proceedings of the 5th conference on USENIX Conference on Object-Oriented Technologies & Systems - Volume 5
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We present the design of a high performance ATM host-network interface for multimedia workstations and servers. At Washington University, as part of an ARPA-sponsored gigabit local ATM testbed, we are building a prototype of this interface that can support a sustained aggregate bidirectional data rate of 2.4 Gbps. The centerpiece of our interface design is a custom chip called the APIC (ATM port interconnect controller). Multiple such chips can be interconnected to yield a desk-area network (DAN) which would serve as a high speed I/O interconnect for the host computer. This paper details the internal design of the APIC chip, and outlines some of its key features. Noteworthy among these are: connection caching, transmit pacing, cell batching, remote control, and support for AAL-0, AAL-5, multipoint, and loopback connections. We have chosen to defer to a later paper the details pertaining to several other features which provide support for zero-copy, improved interrupt handling, direct control of the chip from user-space, and efficient buffering and demultiplexing.