Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
ARM Architecture Reference Manual
ARM Architecture Reference Manual
The Proteus Processor - A Conventional CPU with Reconfigurable Functionality
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Stream Computations Organized for Reconfigurable Execution (SCORE)
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
An augmented reality system with a coarse-grained reconfigurable device
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
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Until now, the lack of software and hardware compatibility between existing reconfigurable processors make them less competitive with hard-wired processors for mainstream computing. In this paper we propose a reconfigurable processor architecture based on the von-Neumann computing model, so that software compatibility can be achieved with minimal work. Furthermore, the proposed processor takes advantage of key features of some FPGAs like partial and dynamic reconfiguration to load on-the-fly a variable number of different coarse-grained execution units.