Guided self-scheduling: A practical scheduling scheme for parallel supercomputers
IEEE Transactions on Computers
Dependence analysis for subscripted variables and its application to program transformations
Dependence analysis for subscripted variables and its application to program transformations
Experience with a performance analyzer for multithreaded applications
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Future general purpose supercomputer architectures
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Wide format floating-point math libraries
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Effects of Loop Fusion and Statement Migration on the Speedup of Vector Multiprocessors
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Parallelism in a multi-user environment
Parallel Computing
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The C240, a tightly coupled, shared memory, parallel/multi-processor, supports up to 4, 40-nanosecond ECL/CMOS Cray-like processors. Managed by a fully semaphored UNIX operating the C240, it can support up to 4 gigabytes of directly addressable physical memory. CONVEX proprietary compiler technology provides automatic vectorization and parallelization for FORTRAN, C, and ADA. Allocation of parallel threads to physical processors is managed by an innovation approach ASAP (Automatic Self-Allocating Processors). ASAP dynamically allocates and deallocates parallel threads to the processors.In creating a second generation supercomputer, several factors were considered prior to commencing design. Among these factors are:Performance - Scalar/Vector/Parallel.Parallel processing efficiency.Semiconductor technology.Compiler optimization strategies.With these factors in mind, the C240 system evolved. The salient features of the C240 are:Tightly coupled, MIMD processor system. Where each processor, up to 4, is a general purpose scientific processor, with a 4 gigabyte virtual address space. Operands are addressed at the byte level.Each processor is a 40 nanosecond, ECL/CMOS implementation of the CONVEX C1, Cray-like, instruction set architecture (see WALLACH 85). Additional instructions were added, in a super-set manner using pre-existing spare opcodes. These instructions provide vector conversions, vector shifts, vector square root, and fully pipelined operations under mask. Additional scalar instructions were added mainly in the area of intrinsics: Sin, Cos, etc.A set of parallel processing instructions was also added and will be discussed in more detail later.A very high bandwidth, 800 Mbytes/sec, multiported memory system capable of supporting up to 4 gigabytes of directly addressable physical memory.Revisions of CONVEX's proprietary compiler technology that support automatic parallelism for Fortran, C and ADA.A fully semaphored UNIX kernel. The UNIX kernel was modified extensively to support multiple simultaneous system calls to different resources and the management of CONVEX's parallel processing paradigm.Lastly, a new and innovative concept for the allocation and scheduling of parallel processes and threads is supported. This unique concept, ASAP, (Automatic Self-Allocating Processors), is a distributed mechanism that permits physical processors to dynamically associate and disassociate themselves from an executing process.