Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Distinguishing Exponent Digits by Observing Modular Subtractions
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
Montgomery in Practice: How to Do It More Efficiently in Hardware
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
Selecting Cryptographic Key Sizes
PKC '00 Proceedings of the Third International Workshop on Practice and Theory in Public Key Cryptography: Public Key Cryptography
A Scalable Architecture for Montgomery Multiplication
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
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In this paper we describe an efficient and secure hardware implementation of the RSA cryptosystem. Modular exponentiation is based on Montgomery's method without any modular reduction achieving the optimal bound. The presented systolic array architecture is scalable in several parameters which makes it possible to implement Compaq's MultiPrime™ in a very efficient way. According to a developed performance model the influence of different parameters is investigated. This platform is optimised for Multiprime as an example for the RSA cryptosystem. In this work we give details about this scheme, which uses three or more factors of the composite. N. Security of this scheme, related to this architecture is also presented.