A fast task-to-processor assignment heuristic for real-time multiprocessor DSP applications

Authors:
John W. Chinneck;Vitoria Pureza;Rafik A. Goubran;Gerald M. Karam;Marco Lávoie
Affiliations:
Systems and Computer Engineering, Carleton University, 4456 Mackenzie building, 1125 Colonel Drive, Ottawa, Ont., Canada K1S 5B6;Departamento de Engenharia de Producao, Universidade Federal de São Carlos, São Carlos, SP, Brazil;Systems and Computer Engineering, Carleton University, 4456 Mackenzie building, 1125 Colonel Drive, Ottawa, Ont., Canada K1S 5B6;Innovative Services Research, AT&T Laboratories, Florham Park, NJ;Institut de la Haute Technologie, La Cité Collégiale, Ottawa, Ont., Canada
Venue:
Computers and Operations Research
Year:
2003

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Abstract

The optimal assignment of the tasks to the processors to minimize total delay in a multiprocessor digital signal processing (DSP) architecture is extremely difficult, particularly for systems of many (e.g. 100) tasks. Two factors especially complicate the problem: (1) the multiprocessor architecture affects the inter-processor communication times, and (2) the specific assignment of tasks to processors affects the inter-task communication times. We develop a fast heuristic for assigning tasks to processors. There are two main ingredients in our method: (i) the choice of a useful general-purpose multiprocessor architecture for DSP applications, and (ii) an adaptive list-ordering heuristic which takes advantage of knowledge of the inter-processor communication characteristics of the chosen architecture. Examples are given, including comparisons to exact branch-and-bound methods, and a large sonar example.