On mask layout partitioning for electron projection lithography

  • Authors:

  • Ruiqi Tian;Ronggang Yu;Xiaoping Tang;D. F. Wong

  • Affiliations:

  • Motorola Inc., Austin, TX;University of Texas at Austin, Austin, TX;Silicon Perspective, a Cadence Company, San Jose, CA;University of Illinois at Urbana-Champaign, Urbana, IL

  • Venue:
  • Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 2002

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Abstract

Electron projection lithography (EPL) is a leading candidate for next generation lithography (NGL) in VLSI production. The membrane mask used in EPL is divided into sub-fields by struts for structural support. A layout must be partitioned into these sub-fields on mask and then stitched back together by the EPL tool on wafer. To minimize possible stitching errors, partitioning of a mask layout should minimize cuts of layout features in the overlapping area between two adjacent sub-fields. This paper presents the first formulation of the mask layout partitioning problem for EPL as a graph problem. The graph formulation is optimally solved with a shortest path approach. Two other techniques are also presented to speed up computation. Experimental runs on data from a real industry design show excellent results.