The capability maturity model: guidelines for improving the software process
The capability maturity model: guidelines for improving the software process
METRICS: a system architecture for design process optimization
Proceedings of the 37th Annual Design Automation Conference
“Timing closure by design,” a high frequency microprocessor design methodology
Proceedings of the 37th Annual Design Automation Conference
Principles of Verifiable RTL Design
Principles of Verifiable RTL Design
Generating Test Data with Enhanced Context-Free Grammars
IEEE Software
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Silicon Access Networks taped out in one year four high performance SoC products: a high-end Network Processor and three associated Co-processors, providing the industry with the highest performance OC-192 Data Plane Processing solution. The four chips are shipping for revenue and went into production from first silicon with no mask change. They were designed using state-of-the-art 0.13μm technology and collectively represent about 750-million transistors, implementing a variety of analog, digital, high-speed memory and functional blocks. This contribution describes the design of the Packet Processor and some of the key aspects of Silicon Access Networks' design methodology that enabled to accomplish repeatable "first pass silicon" successes, despite system complexity challenges. The 175-million transistor iPP was simultaneously designed in three locations (San Jose/CA, Raleigh/NC, Ottawa/Canada). Bring-up and pre-production showed that first silicon met all its targets: power, speed, yield and complete functionality.