IEEE Transactions on Computers
Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults
IEEE Transactions on Computers
Cryptographic key reliable lifetimes: bounding the risk of key exposure in the presence of faults
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
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High reliability is a desirable property of any implementation of the Advanced Encryption Standard. To achieve high reliability all possible faults must be detected to avoid the use and transmission of erroneous encrypted/decrypted data. In this paper we first study the behavior of faults which may occur during the encryption and decryption procedures of AES, and the way such faults eventually propogate to the final result. We then describe an appropriate detection technique for these faults.This work extends our preliminary results [1] by considering more general fault models (e.g., Permanent and multiple transient faults), and the possibility of fault masking.