Proof systems for satisfiability in Hennessy-Milner logic with recursion
Theoretical Computer Science - Special issue on the Thirteenth Colleque sur les Arbres en Alge`bre et en Programmation Nancy, March 1988
Real-time behaviour of asynchronous agents
CONCUR '90 Proceedings on Theories of concurrency : unification and extension: unification and extension
Bisimulation through probabilistic testing
Information and Computation
Minimum and maximum delay problems in real-time systems
Formal Methods in System Design - Special issue on computer-aided verification: special methods I
Model-checking in dense real-time
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
Theoretical Computer Science
Characteristic formulae for processes with divergence
Information and Computation
Journal of the ACM (JACM)
What's decidable about hybrid automata?
STOC '95 Proceedings of the twenty-seventh annual ACM symposium on Theory of computing
UPPAAL—a tool suite for automatic verification of real-time systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Frontier between decidability and undecidability: a survey
Theoretical Computer Science - Special issue on universal machines and computations
Communication and Concurrency
On the temporal analysis of fairness
POPL '80 Proceedings of the 7th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
From Timed Automata to Logic - and Back
MFCS '95 Proceedings of the 20th International Symposium on Mathematical Foundations of Computer Science
CMC: A Tool for Compositional Model-Checking of Real-Time Systems
FORTE XI / PSTV XVIII '98 Proceedings of the FIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XI) and Protocol Specification, Testing and Verification (PSTV XVIII)
Model Checking via Reachability Testing for Timed Automata
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Compositional Model Checking of Real Time Systems
CONCUR '95 Proceedings of the 6th International Conference on Concurrency Theory
The Power of Reachability Testing for Timed Automata
Proceedings of the 18th Conference on Foundations of Software Technology and Theoretical Computer Science
Kronos: A Model-Checking Tool for Real-Time Systems
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Decidability of Bisimulation Equivalences for Parallel Timer Processes
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Automated Analysis of an Audio Control Protocol
Proceedings of the 7th International Conference on Computer Aided Verification
Verification of an Audio Protocol with Bus Collision Using UPPAAL
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
STARI: A Case Study in Compositional and Hierarchical Timing Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Modeling and verification of parallel processes
LICS '95 Proceedings of the 10th Annual IEEE Symposium on Logic in Computer Science
Two examples of verification of multirate timed automata with Kronos
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Undecidability Results for Hybrid Systems
Undecidability Results for Hybrid Systems
Real-time specification patterns
Proceedings of the 27th international conference on Software engineering
Modal logics for timed control
CONCUR 2005 - Concurrency Theory
A new modality for almost everywhere properties in timed automata
CONCUR 2005 - Concurrency Theory
On-the-fly TCTL model checking for time Petri nets
Theoretical Computer Science
A Compositional Translation of Timed Automata with Deadlines to Uppaal Timed Automata
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
Checking Timed Büchi Automata Emptiness Using LU-Abstractions
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
Liveness Checking as Safety Checking for Infinite State Spaces
Electronic Notes in Theoretical Computer Science (ENTCS)
Adapting the UPPAAL model of a distributed lift system
FSEN'07 Proceedings of the 2007 international conference on Fundamentals of software engineering
Efficient detection of Zeno runs in timed automata
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
Accomplishing approximate FCFS fairness without queues
HiPC'07 Proceedings of the 14th international conference on High performance computing
Observing continuous-time MDPs by 1-clock timed automata
RP'11 Proceedings of the 5th international conference on Reachability problems
Model checking duration calculus: a practical approach
ICTAC'06 Proceedings of the Third international conference on Theoretical Aspects of Computing
Decompositional reasoning about the history of parallel processes
FSEN'11 Proceedings of the 4th IPM international conference on Fundamentals of Software Engineering
Composing real-time concurrent objects: refinement, compatibility and schedulability
FSEN'11 Proceedings of the 4th IPM international conference on Fundamentals of Software Engineering
Modeling and verification of hybrid dynamic systems using multisingular hybrid Petri nets
Theoretical Computer Science
Modeling and verifying hierarchical real-time systems using stateful timed CSP
ACM Transactions on Software Engineering and Methodology (TOSEM)
A formal framework to specify and verify real-time properties on critical systems
International Journal of Critical Computer-Based Systems
| Hi-index | 5.23 |
The computational engine of the verification tool UPPALL consists of a collection of efficient algorithms for the analysis of teachability properties of systems. Model-checking of properties other than plain reachability ones may currently be carried out in such a tool as follows. Given a property φ to model-check, the user must provide a test automaton Tφ for it. This test automaton must be such that the original system S has the property expressed by φ precisely when none of the distinguished reject states of Tφ can be reached in the synchronized parallel composition of S with Tφ. This raises the question of which properties may be analysed by UPPAAL in such a way. This paper gives an answer to this question by providing a complete characterization of the class of properties for which model-checking can be reduced to reachability testing in the sense outlined above. This result is obtained as a corollary of a stronger statement pertaining to the compositionality of the property language considered in this study. In particular, it is shown that our language is the least expressive compositional language that can express a simple safety property stating that no reject state can ever be reached.Finally, the property language characterizing the power of reachability testing is used to provide a definition of characteristics properties with respect to a timed version of the ready simulation preorder, for nodes of τ-free, deterministic timed automata.