Accelerating Adobe Photoshop with the Reconfigurable Logic
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A PCI bus simulation framework and some simulation results on PCI Standard 2.1 latency limitations
Journal of Systems Architecture: the EUROMICRO Journal
Multiple Precision for Resource Minimization
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient Load Balancing on a Cluster for Large Scale Online Video Surveillance
ICDCN '09 Proceedings of the 10th International Conference on Distributed Computing and Networking
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper presents the SONIC reconfigurable computing architecture and the first implementation, SONIC-1. SONIC is designed to support a software plug-in methodology to accelerate video image processing applications. SONIC differs from other architectures through the use of Plug-In Processing Elements (PIPEs) and the Application Programmer's Interface (API). Each PIPE contains a reconfigurable processor, a scalable router that also formats video data, and a frame-buffer memory. The SONIC architecture integrates multiple PIPEs together using a specialized bus structure which enables flexible and optimal pipelined processing. SONIC-1 communicates with the host PC through the PCI bus and has 8 PIPEs. We have developed an easy to use API which allows SONIC-1 to be used by multiple applications simultaneously. Preliminary results show that a 19 tap separable 2-D FIR filter implemented on a single PIPE achieves processing rates of more than 15 frames per second operating on 512 x 512 video transferred over the PCI bus. We estimate that using all 8 PIPEs, we could obtain real-time processing rates for complex operations such as image warping.