The duality of memory and communication in the implementation of a multiprocessor operating system
SOSP '87 Proceedings of the eleventh ACM Symposium on Operating systems principles
Comments on “ `Coherency for multiprocessor virtual addresses caches' by James R. Goodman"
ACM SIGARCH Computer Architecture News
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Multilanguage Parallel Programming of Heterogeneous Machines
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Compiler Optimizations for Enhancing Parallelism and Their Impact on Architecture Design
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
The VMP multiprocessor: initial experience, refinements, and performance evaluation
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
TLB consistency on highly-parallel shared-memory multiprocessors
Proceedings of the Twenty-First Annual Hawaii International Conference on Architecture Track
UNIX system V-386 programmer's reference manual
UNIX system V-386 programmer's reference manual
Performance of the VAX-11/780 translation buffer: simulation and measurement
ACM Transactions on Computer Systems (TOCS)
Architecture independent virtual memory management for parallel and distributed environments: the mach approach
SOSP '89 Proceedings of the twelfth ACM symposium on Operating systems principles
A portable interface for on-the-fly instruction space modification
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Virtual memory primitives for user programs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Limits to low-latency communication on high-speed networks
ACM Transactions on Computer Systems (TOCS)
High-bandwidth address translation for multiple-issue processors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Synchronization and communication in the T3E multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Cashmere-2L: software coherent shared memory on a clustered remote-write network
Proceedings of the sixteenth ACM symposium on Operating systems principles
ACM Transactions on Computer Systems (TOCS)
IEEE Transactions on Computers
Lazy TLB Consistency for Large-Scale Multiprocessors
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
A portable kernel abstraction for low-overhead ephemeral mapping management
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
A caching model of operating system kernel functionality
OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
RadixVM: scalable address spaces for multithreaded applications
Proceedings of the 8th ACM European Conference on Computer Systems
A new perspective for efficient virtual-cache coherence
Proceedings of the 40th Annual International Symposium on Computer Architecture
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We discuss the translation lookaside buffer (TLB) consistency problem for multiprocessors, and introduce the Mach shootdown algorithm for maintaining TLB consistency in software. This algorithm has been implemented on several multiprocessors, and is in regular production use. Performance evaluations establish the basic costs of the algorithm and show that it has minimal impact on application performance. As a result, TLB consistency does not pose an insurmountable obstacle to multiprocessors with several hundred processors. We also discuss hardware support options for TLB consistency ranging from a minor interrupt structure modification to complete hardware implementations. Features are identified in current hardware that compound the TLB consistency problem; removal or correction of these features can simplify and/or reduce the overhead of maintaining TLB consistency in software.