An in-cache address translation mechanism
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Translation lookaside buffer consistency: a software approach
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
SOSP '89 Proceedings of the twelfth ACM symposium on Operating systems principles
Experiences from multithreading System V Release 4
SEDMS III Papers from the symposium on Experiences with distributed and multiprocessor systems
Lazy release consistency for software distributed shared memory
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Design tradeoffs for software-managed TLBs
ACM Transactions on Computer Systems (TOCS)
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Software Mechanisms for Multiprocessor TLB Consistency
Software Mechanisms for Multiprocessor TLB Consistency
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The memory system performance heavily depends on the eflciency of a translation lookaside bufSer(TLB), a cache for fast address translation. Recent trends towards multiprocessing as well as modular software structure impose more stress on TLBs, since consistency among multiple TLBs should be maintained. However, previous TLB consistency schemes do not seem suitable for large-scale multiprocessors, because they require interprocessor interrupts which are extremely harmful to the overall system performance. In this paper, we propose a lazy TLB scheme for large-scale multiprocessors. By exploiting the potential of lazy release consistency, the scheme postpones the TLB synchronization until the time of an acquire access to the shared data. This scheme allows a processor to invalidate remote TLBs asynchronously, and eliminates the need for interprocessor interrupts. Simulation results show that the lazy TLB scheme is very efficient for large-scale multiprocessors.