Information content of CPU memory referencing behavior
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Retrospective: a low-overhead coherence solution for multiprocessors with private cache memories
25 years of the international symposia on Computer architecture (selected papers)
Performance Tradeoffs in Multithreaded Processors
IEEE Transactions on Parallel and Distributed Systems
Multiprocessor hardware: An architectural overview
ACM '80 Proceedings of the ACM 1980 annual conference
Staged circuit switching for network computers
SIGCOMM '83 Proceedings of the symposium on Communications Architectures & Protocols
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A general-purpose multiple-stream processor with shared memory and a single time-multiplexed synchronous bus has been implemented. The AMP-1 system uses eight standard microprocessors and 64K bytes of memory. The design is highly efficient in the use of processor, bus, and memory resources. Preliminary performance measurements agree closely with an analytic memory access conflict model and show extremely low conflict-based performance degradation. Heavy interleaving of the memory and effective multitasking of a job can yield significant performance speedups. Considerations for future implementations are presented.