Symbolic execution and program testing
Communications of the ACM
VLSI test expertise system using a control flow model
DAC '84 Proceedings of the 21st Design Automation Conference
CADOC: a system for computed aided functional test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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A top down design methodology of VLSI Circuits used at the University of Grenoble is briefly presented. The choice of a data path is analyzed with respect to testability and diagnosability requirements. Design modifications (in terms of special test control) help achieves the testability requirements. Such an approach helps to avoid costly techniques like additional scan pathes (LSSD, Bilbo) Combined with dynamic analysis techniques (Stroboscopic analysis), this approach produces efficient VLSI tests.