Symbolic execution and program testing
Communications of the ACM
Hardware description levels and test for complex circuits
DAC '81 Proceedings of the 18th Design Automation Conference
Top down design and testability of VLSI circuits
DAC '82 Proceedings of the 19th Design Automation Conference
Symbolic simulation for correct machine design
DAC '79 Proceedings of the 16th Design Automation Conference
The application of program verification techniques to hardware verification
DAC '79 Proceedings of the 16th Design Automation Conference
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The automatic generation of test programs for VLSI circuits and systems remains an unanswered wish. The solution seems to be a computerized expert aid, integrated in a whole system for circuit design. This paper outlines the concepts of an intelligent agent whose aims are to help the designer in appraising the diagnosability of the device or the system under design, to suggest design modifications, to generate test patterns for elementary modules and to assemble the basic test sequences into a test program for the whole circuit. Emphasis is put in this paper on this last task, especially for systems described by a control flow model (CADOC language) which is suitable for VLSI circuits like general purpose or dedicated micro-processors, distributed controllers, etc... The CAT system works like an intelligent assistant for test program generation and like an expert system for the diagnosis on the chip.