Winner-take-all networks of O(N) complexity
Advances in neural information processing systems 1
Analog Integrated Circuits and Signal Processing - Special issue: low-voltage low-power analog integrated circuits
Active pixel sensor design: from pixels to systems
CMOS imagers
Image Recognition in Analog VLSI with On-Chip Learning
ICANN '09 Proceedings of the 19th International Conference on Artificial Neural Networks: Part I
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A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the gm/ID methodology. As it will be shown, this method allows a rapid new dimensioning when specifications are modified. Both the WTA and the LTA can operate with low voltage supply, and show better speed characteristics (delay and raising time) for a 6 bits accuracy and a typical consumption of 50 mW/cell than previous realisations.