Variability in the execution of multimedia applications and implications for architecture
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Efficient longest executable path search for programs with complex flows and pipeline effects
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Deadline analysis of interrupt-driven software
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
Clustered calculation of worst-case execution times
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Deadline Analysis of Interrupt-Driven Software
IEEE Transactions on Software Engineering
Clustered Worst-Case Execution-Time Calculation
IEEE Transactions on Computers
Automated Testing of Timeliness: A Case Study
AST '07 Proceedings of the Second International Workshop on Automation of Software Test
Identifying irreducible loops in the Instrumentation Point Graph
Journal of Systems Architecture: the EUROMICRO Journal
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In the development of embedded hard real-time systems the ability to guarantee worst case execution times is gaining importance and complexity. The fast evolving processor acceleration techniques constantly increase the gap between a processor which uses the accelerations and one which does not. Modeling cache, pipelines and other parts of the processor gets increasingly difficult and time consuming. To circumvent this problem especially in the domain of rapid prototyping of embedded hard real-time systems, we propose to lay more weight on measurement and less on modeling. By analyzing the control flow graph the compiler uses for optimization, a reduced control flow graph can be generated, which limits the paths to be measured. Using this information the object code of the program is being instrumented and then measured. By measuring all paths the reduced control flow graph indicates, predictability is achieved without using too pessimistic estimations.