Discrete cosine transform: algorithms, advantages, applications
Discrete cosine transform: algorithms, advantages, applications
The JPEG still picture compression standard
Communications of the ACM - Special issue on digital multimedia systems
VLSI Algorithms and Architectures
VLSI Algorithms and Architectures
JPEG Still Image Data Compression Standard
JPEG Still Image Data Compression Standard
A Storage Efficient Way to Implement the Discrete Cosine Transform
IEEE Transactions on Computers
On Computing the Discrete Cosine Transform
IEEE Transactions on Computers
A prototype VLSI chip architecture for JPEG image compression
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Stride Permutation Networks for Array Processors
Journal of VLSI Signal Processing Systems
SACTA: a self-adjusting clock tree architecture for adapting to thermal-induced delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
In this paper, we describe a fully pipelined single chip VLSI architecture for implementing the JPEG baseline image compression standard The architecture exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The architecture for discrete cosine transform and the entropy encoder are based on efficient algorithms designed for high speed VLSI implementation. The entire architecture can be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024/spl times/1024 color images. Currently, a prototype CMOS VLSI chip implementing the proposed architecture is being designed.