Depth-first iterative-deepening: an optimal admissible tree search
Artificial Intelligence
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Best-first search with controlled time and storage
Best-first search with controlled time and storage
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Journal of the ACM (JACM)
Iterative deepening multiobjective A*
Information Processing Letters
A New Approach to Iterative Deepening Multiobjective A*
AI*IA '09: Proceedings of the XIth International Conference of the Italian Association for Artificial Intelligence Reggio Emilia on Emergent Perspectives in Artificial Intelligence
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Speeding up logic simulation is important to reduce design time of complex systems. Hardware emulation through reconfigurable systems (RS) built using FPGA's offer an cheap and efficient method to achieve the required speed-up. Emulation through RS poses some unique problems because of the limited circuit and I/O resources. A preparatory step for emulation using RS is to partition the circuit into as few parts as possible satisfying the resource constraints. This paper presents multi-objective search based optimal and approximate algorithms for circuit partitioning for this purpose.