Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment
IEEE Transactions on Computers
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Clock rate versus IPC: the end of the road for conventional microarchitectures
Proceedings of the 27th annual international symposium on Computer architecture
The TigerSHARC DSP Architecture
IEEE Micro
Exploring the Design Space of Future CMPs
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Efficient Interconnects for Clustered Microarchitectures
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Interface Synthesis: Issues and Approaches
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
POWER4 system microarchitecture
IBM Journal of Research and Development
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This paper quantifies the performance of typical functionalunit interface designs in single-chip systems. Weintroduce a specific equation to guide the design of optimalmodule interfaces. We show how the equation andinterface considerations lead to more efficient queuestructures for request buffering. For a specific single-chipdesign, we use simulation to show that: 1) For low requestrates, queue structure is relatively unimportant to eithersystem request bandwidth or service latency; 2) For a narrowrange of request rates, queue structure has a significantimpact on system latency but not bandwidth; 3) Forhigh request rates, queue structure impacts bandwidth significantly;4) As request service latencies increase relativeto the queue size, the impact of the queue structuredecreases; 5) Given a particular range of request rates,the complexity of particular queue structures can betraded off with the desired system bandwidth and latencyperformance. For a particular single-chip system, a maximum29% bandwidth improvement and 60% latencyimprovement are achieved when using the more efficientqueue structures.