Efficient Polygon Clipping for an SIMD Graphics Pipeline
IEEE Transactions on Visualization and Computer Graphics
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
ManArray Processor Interconnection Network: An Introduction
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Embedded processor design challenges
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IBM Mwave/sup TM/ has developed a radically new approach for real-time video and graphics processing. A scalable array of processing elements (PEs) is configured as a "folded array" for effective execution of matrix and transpose operations. The single chip Mwave Folded Array Signal Transform processor (MFAST) is a scalable DSP that provides 10+ billion 16-bit operations-per-second@50 MHz, sustainable during algorithm execution. This paper describes key M.F.A.S.T. elements and a bounded 18-22 cycle 8/spl times/8-pixel 2-D discrete cosine transform (DCT) program, verified on VHDL and functional simulator models.