Reconfigurable scan chains: a novel approach to reduce test application time
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Control Strategies for Chip-Based DFT/BIST Hardware
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
CTL the language for describing core-based test
Proceedings of the IEEE International Test Conference 2001
Proceedings of the IEEE International Test Conference 2001
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Typically the DFT features are decidedduring the design and remain fixed after thedesign is completed. This makes a devicetestable only on ATEs, which can satisfy thetest requirements for that chip. If such anATE is not available then the IC eithercannot be fully tested, or ATE resources arewasted when it is designed for lesscapabilities. This paper presents amethodology that builds on the testerretargetable pattern technology for testingICs on testers with different pin capabilitiesSuch a capability would be an essentialelement in reduced pin-count (multi-site)testing. The interfacing needs between theTest Automation World and the TesterEnvironment are also developed in thispaper.